Hardware/Software co-designed systems may leverage dynamic binary optimization to improve performance. For dynamic binary optimization on memory instructions, memory alias information may be required. Dynamic binary optimization may leverage hardware alias checking for speculative memory optimization in an atomic region. When a load instruction is speculatively reordered before a store instruction with possible memory alias between them, the load instruction may need to set up an alias protection register with its memory address stored in it. In response to the store instruction being executed, the store instruction may check against the alias protection register with its memory address to detect mis-speculations. Mis-speculations may lead to the rollback of the whole region and re-execution of non-optimized or less-optimized code.